Posted On: SEP-2026 | Categories : Semiconductor and Electronics
TSMC’s decision to double CoWoS capacity in 2025 exposed a major change in the AI semiconductor supply chain: producing an advanced logic die is no longer enough to deliver a finished accelerator. The processor must also be integrated with high-bandwidth memory, interposers, substrates, power-delivery structures and cooling systems before it becomes a saleable computing product. When any of these packaging components lacks qualified capacity, completed wafers can wait for downstream assembly, delaying shipments and limiting revenue recognition.
This production constraint explains why advanced packaging has moved closer to the centre of semiconductor investment. TSMC allocated 10% to 20% of its USD 38–42 billion 2025 capital budget to advanced packaging, testing, mask-making and related capabilities. Depending on the final spending level, the combined allocation represented approximately USD 3.8–8.4 billion. Intel is expanding EMIB and Foveros, Micron is building an approximately USD 7 billion HBM packaging facility in Singapore, and the U.S. government has committed USD 1.4 billion to next-generation packaging research and infrastructure.
The commercial challenge in advanced packaging extends far beyond integrating multiple dies into a single package. The industry is now dealing with a new class of manufacturing complexity where packaging decisions directly influence processor performance, cost structure, and supply-chain resilience. Manufacturers must demonstrate the ability to qualify large multi-die systems at scale while securing critical inputs such as advanced substrates and high-bandwidth memory (HBM). At the same time, they need to manage thermal stress, package warpage, signal integrity, buried defect detection, and yield optimization across increasingly complex architectures. As chip designs move toward heterogeneous integration, advanced packaging is no longer a downstream assembly step; it has become a strategic component of semiconductor architecture, production economics, and long-term capacity planning.
AI accelerators require large numbers of processing cores to access enormous datasets without waiting for conventional external memory connections. High-bandwidth memory addresses this problem by stacking memory dies vertically and positioning them close to the compute processor. Advanced packaging connects the memory and logic through short, wide electrical pathways that provide substantially more bandwidth than traditional circuit-board connections.
Lam Research’s breakdown of NVIDIA’s H100 shows how packaging complexity translates into supply-chain exposure. The processor combines one GPU with six HBM stacks through a CoWoS-based structure. A finished H100 therefore depends on the availability and successful integration of the GPU die, multiple memory stacks, an interposer, a high-density substrate and package-level cooling. A shortage or yield problem affecting any one component can restrict shipment of the entire accelerator, even when GPU wafers are available.
TSMC’s capacity disclosures demonstrate how quickly packaging moved into the AI supply bottleneck. During its April 2025 earnings call, the company stated that it was working to double its CoWoS capacity during 2025. TSMC also expected revenue from AI accelerators—which it defines as AI GPUs, AI application-specific integrated circuits and HBM controllers—to double during the year. Packaging capacity was therefore expanding alongside leading-edge wafer production rather than remaining a secondary back-end consideration.
Announced packaging capacity should not be interpreted as immediately available output. New tools must be installed, calibrated and qualified for specific customer designs before they contribute saleable volume. Substrates, interposers, HBM and thermal components must also arrive in matched quantities. A facility can therefore possess installed equipment while remaining constrained by customer qualification, material availability or package yield. For customers, usable CoWoS capacity is more important than nominal tool capacity because only qualified lines can support revenue-producing accelerator shipments.
TSMC allocated between USD 38 billion and USD 42 billion for 2025 capital expenditure. Approximately 10% to 20% was designated for advanced packaging, testing, mask-making and related capabilities. At the lower end of both ranges, that allocation would represent approximately USD 3.8 billion; at the upper end, it could reach USD 8.4 billion. Although TSMC does not separate packaging from testing and mask-making in this disclosure, the scale shows how much capital the company is directing toward the infrastructure surrounding advanced wafers.
Chiplet architectures create economic value only when the benefits of modular design outweigh the additional complexity introduced at the package level. Their advantage comes from allowing manufacturers to optimize each functional block independently — using advanced nodes for high-performance compute elements while relying on mature, cost-efficient processes for analogue, I/O, memory interface, and power-management components. This approach improves wafer economics by reducing the exposure of expensive leading-edge silicon to defect-related losses and enables companies to reuse validated chiplets across multiple product generations.
However, chiplet-based designs do not automatically reduce costs. The shift from a monolithic die to a multi-die system transfers some complexity from wafer manufacturing into packaging, integration, validation, and testing. Every additional die-to-die connection introduces requirements for higher interconnect reliability, interface verification, thermal management, and system-level testing. As a result, the economic benefit depends on achieving sufficient scale, design reuse, and manufacturing efficiency. Chiplets deliver the greatest value when they allow companies to mix and match proven components, accelerate product development cycles, and avoid the yield limitations of increasingly large monolithic processors while maintaining acceptable package costs and performance targets.
Intel’s Data Center GPU Max Series demonstrates the scale of integration that packaging can support. The product combines 47 active tiles manufactured across five process nodes and contains more than 100 billion transistors. Its significance lies less in the tile count than in the manufacturing flexibility: Intel can select different processes for compute, memory, input/output and connectivity functions instead of forcing the entire system onto one node.
This delivers expert evaluation because it explains when chiplets provide an economic advantage and when package costs can offset that advantage.
In 2.5D packaging, logic and memory dies are placed beside one another on an interposer or high-density redistribution structure. This arrangement supports wide, short connections without stacking every active component vertically. It is commercially established in high-performance computing because it allows multiple HBM stacks to surround a GPU or custom accelerator while providing sufficient surface area for power delivery and cooling.
TSMC’s CoWoS and Intel’s EMIB illustrate two different production strategies. CoWoS uses an interposer-based structure to connect logic and memory before the assembly is mounted on a substrate. EMIB uses localized embedded silicon bridges, reducing the amount of silicon required beneath the package. Both approaches seek to overcome the communication and size limitations of monolithic processors, but they have different implications for routing density, package dimensions, cost and manufacturing complexity.
CoWoS and other 2.5D approaches are already supporting high-volume AI and high-performance-computing products. Through-silicon-via memory stacking is established in HBM production. Logic-on-logic hybrid bonding is moving into early commercial deployment, while panel-level processing and co-packaged optics remain less mature and require additional manufacturing qualification. Glass substrates sit between these categories: equipment and material development are advancing, but broad high-volume adoption has not yet been demonstrated.
TSMC’s packaging roadmap is moving beyond conventional size limitations. The company’s CoWoS platform includes variants for interposers larger than 3.3 times the standard reticle area. Its 2025 reporting stated that a CoWoS solution using an interposer measuring 5.5 times the reticle size had been certified, with volume production scheduled to begin in 2026.
Moving beyond the reticle limit allows manufacturers to combine more compute dies and HBM stacks within one system. However, larger interposers increase substrate complexity, warpage, cooling requirements and yield risk. A defect affecting an interposer, substrate or connection can compromise multiple high-value dies. The ability to manufacture a large package consistently—not merely design one—has therefore become a competitive advantage.
In 3D integration, active dies are stacked directly above one another. Through-silicon vias and fine-pitch connections reduce the distance that data must travel, increasing bandwidth density and lowering the energy consumed per transferred bit. TSMC’s SoIC platform supports chip-on-wafer and wafer-on-wafer configurations and begins its bonding-pitch roadmap below 10 micrometres. TSMC reported that its 3-nanometre chip-stacking technology entered volume production in 2025, indicating that vertical integration is progressing from qualification into commercial manufacturing.
Intel’s Foveros platform places chiplets on an active base die, while Foveros Direct uses copper-to-copper hybrid bonding to create denser and lower-resistance connections. Intel can combine Foveros with EMIB in a 3.5D architecture, allowing several horizontally connected and vertically stacked components to operate within the same package.
Conventional 3D assemblies commonly use solder microbumps to connect dies. As interconnect pitches become smaller, these bumps consume valuable surface area and introduce resistance, capacitance and manufacturing limitations. Hybrid bonding joins dielectric surfaces and copper contacts directly, eliminating conventional solder bumps while creating shorter and denser electrical connections.
Hybrid bonding is particularly relevant to logic-on-logic stacking, HBM, image sensors, processor-memory integration and future optical devices. It reduces the physical distance between components, which can increase data-transfer speed and lower the power consumed by die-to-die communication.
Equipment investment provides stronger evidence of commercial maturity than technology roadmaps alone. In April 2025, Applied Materials purchased a 9% stake in BE Semiconductor Industries after the companies had collaborated since 2020 on die-based hybrid bonding. Their integrated system combines Applied Materials’ surface-preparation and wafer-processing capabilities with Besi’s die-placement technology.
The development of hybrid bonding highlights how advanced packaging is changing the traditional boundary between semiconductor fabrication and assembly. Techniques once associated primarily with front-end wafer manufacturing — including ultra-clean surface preparation, chemical processing, planarization, and precision material deposition — are becoming critical elements of package production. As chip architectures move toward three-dimensional stacking and heterogeneous integration, packaging facilities increasingly require semiconductor-level process control rather than conventional assembly capabilities.
However, scaling hybrid bonding from laboratory demonstrations to high-volume manufacturing remains challenging because the process depends on extremely tight control over surface quality, copper uniformity, alignment accuracy, and contamination levels. A minor particle, surface defect, or bonding misalignment can compromise connections that cannot be repaired after stacking. The economic impact is significant because a bonding failure at an advanced stage can result in the loss of multiple high-value dies, including components that have already passed wafer-level testing. This makes inspection, metrology, cleaning, and defect detection critical factors in determining whether hybrid bonding improves overall package performance and cost efficiency or introduces additional manufacturing risk.
Because of this complexity, hybrid bonding adoption is expected to be concentrated initially in applications where performance gains justify higher manufacturing investment. AI accelerators, high-bandwidth memory (HBM), advanced image sensors, and high-performance computing processors benefit from increased interconnect density, lower power consumption, and improved data transfer capability. In these markets, the value created through higher bandwidth and system efficiency can offset the additional process costs, making hybrid bonding a strategic manufacturing technology rather than simply an incremental packaging improvement.
Most advanced packaging processes still rely on circular wafers, but the growing size of AI and high-performance computing packages is exposing the limitations of wafer-based manufacturing. Panel-level processing replaces the circular wafer with a larger rectangular format, allowing more package units to be produced from the same processing area while reducing unused space. This approach could improve material efficiency and throughput as package dimensions continue to expand.
However, panel-level packaging economics depend on more than simply increasing the number of packages per carrier. Manufacturers must achieve consistent performance across the entire panel by controlling warpage, dimensional variation, handling stability, and defect rates. Key evaluation factors include panel standardization, package yield, equipment efficiency, and cost per known-good package. If larger panels introduce higher defect losses or lower process control, the expected efficiency gains may disappear. The commercial success of panel-level packaging will therefore depend on converting higher surface utilization into reliable, high-volume production advantages.
Lam’s ability to process panels as large as 1.1 metres by 1.3 metres demonstrates equipment progress, but TSMC’s description of its panel-level work as a feasibility study shows that industrial readiness remains uncertain. The technology should therefore be treated as an emerging manufacturing route rather than an immediate replacement for wafer-level packaging.
The technology is not yet as mature as CoWoS or established fan-out wafer-level packaging. In September 2026, Lam Research described panel processing as an emerging approach whose principal challenges include uniformity, yield control, automation, throughput and the absence of common panel standards. TSMC had similarly stated in 2025 that its panel-level work remained at the feasibility-study stage. These disclosures distinguish genuine production technologies from promising approaches that still require manufacturing validation.
Equipment capability is advancing rapidly, with suppliers developing tools designed for industrial-scale panel processing. Lam’s Kallisto platform supports fine-line plating below 10 micrometres across organic and glass-core materials and handles panels up to 1.1 metres by 1.3 metres, while its PHOENIX system targets 515-millimetre by 510-millimetre panels with throughput of up to 120 panels per hour.
However, equipment readiness alone does not determine commercial success. Panel-level packaging introduces new manufacturing challenges because larger processing areas amplify risks related to film uniformity, feature control, contamination, handling damage and warpage. Maintaining consistent quality across a panel several times larger than a conventional 300-millimetre wafer will be critical for achieving competitive yields.
The absence of a common panel format also creates uncertainty across the ecosystem, affecting equipment design, material standards, automation and inspection infrastructure. Early adopters must prove that higher area utilization can offset the costs of new tools, process qualification and yield optimization. Ultimately, panel-level packaging will be judged by the cost and reliability of each known-good package, not simply by the number of devices produced per panel.
Organic substrates remain widely used because they are established, scalable and relatively cost-effective. However, increasingly large and dense packages expose limitations related to dimensional stability, fine-line routing, thermal expansion and warpage.
Glass is being developed for core substrates and interposers because its smooth surface and adjustable material properties can support precise electrical routing, controlled thermal expansion and larger package dimensions. It can also accommodate through-glass vias and provide favourable electrical behaviour in high-frequency applications.
Glass adoption will probably begin where package size and routing density create a measurable economic problem for organic substrates. Large AI accelerators, high-performance switches and packages integrating electrical and optical components are stronger early candidates than cost-sensitive consumer devices. These products can absorb higher material and qualification costs when dimensional stability prevents warpage, improves yield or supports additional chiplets.
The key purchasing decision is not based solely on glass substrates offering superior technical performance. Commercial success depends on whether suppliers can deliver consistent substrate quality, equipment providers can scale through-glass via processing efficiently, and manufacturers can maintain package reliability under real operating conditions such as thermal cycling. Adoption will ultimately depend on the performance of the entire manufacturing ecosystem, not the material advantage of glass alone.
Intel has positioned glass substrates as a route to continued transistor and interconnect scaling at the package level later in the decade. Glass could allow manufacturers to place more chiplets and high-density connections within one package without experiencing the same degree of dimensional distortion associated with large organic substrates.
The commercial transition will require more than replacing one material with another. Glass can be brittle, while via formation may require specialized laser or etching systems. Metallization, adhesion, handling and long-term reliability must also be qualified across multiple suppliers and operating environments.
For materials suppliers, substrate manufacturers, laser-equipment providers and plating companies, glass introduces a new qualification pathway covering composition control, via formation, surface processing, metallization and inspection. Adoption is likely to begin in applications where larger package sizes, higher interconnect density and improved dimensional stability justify the cost and complexity of changing established processes.
Panel-level processing and glass substrates could become complementary technologies because glass provides the structural stability required for larger manufacturing formats. However, broad adoption will require alignment across the ecosystem, including equipment compatibility, material standards, panel dimensions and inspection methods. The commercial opportunity will depend on whether the combined benefits translate into reliable high-volume manufacturing rather than only improved technical performance.
AI computing systems increasingly consume power moving data rather than performing calculations. Electrical connections lose signal integrity and require more energy as bandwidth and transmission distance increase. Co-packaged optics addresses this problem by placing optical components on the same substrate as a processor or network switch.
Moving the optical interface closer to the computing element shortens the electrical path before data is converted into light. This can increase input/output bandwidth while reducing communication power, which is especially important in AI clusters containing thousands of accelerators.
For data-centre operators, the value of co-packaged optics will depend on total system economics rather than bandwidth alone. Lower energy per bit can reduce power and cooling costs, but tightly integrated optics may be more difficult to repair than pluggable transceivers. Operators must compare energy savings with replacement costs, service interruption and the financial risk of discarding an expensive switch package after an optical failure.
This trade-off explains why co-packaged optics may first enter tightly controlled hyperscale environments where operators can redesign networking, cooling and maintenance together. Broader adoption will require standardized interfaces and practical repair strategies.
Imec’s optical-interconnect research estimates that placing the optical module on the same substrate as an xPU could reduce link energy toward 5 picojoules per bit or less. Even a small reduction in energy per transferred bit can influence rack-level power consumption, cooling requirements and the operating cost of large data centres.
Commercialization remains challenging because co-packaged optics requires precise integration of photonic dies, lasers, electronic circuits and optical fibres within a tightly controlled package environment. Optical components must operate alongside high-performance logic while maintaining alignment, reliability and thermal stability. A failure in a single optical element can compromise an expensive computing or switching system, increasing the importance of package-level validation.
Manufacturers also need scalable solutions for optical coupling, testing, fibre integration and repair. As a result, co-packaged optics will require coordination across the semiconductor ecosystem, including foundries, OSATs, photonic-component suppliers, connector manufacturers, equipment providers, testing companies and data-centre operators. Its commercial success will depend on building a reliable manufacturing chain rather than advancing any single technology component.
Higher integration density places more power within a smaller volume. In 2.5D systems, localized hotspots can form across large interposers containing logic and memory. In 3D systems, heat generated by a lower die must travel through or around other active components before reaching a cooling structure.
Differences in thermal expansion among silicon, copper, glass, organic substrates, adhesives and thermal materials can also stress fine interconnects during production and repeated operating cycles. As package dimensions increase and connection pitches shrink, small mechanical changes can influence reliability and product life.
These conditions are increasing the value of thermal-interface materials, heat spreaders, vapor chambers, direct liquid cooling, backside power delivery, embedded temperature sensors and package-aware simulation. Advanced foils, engineered polymers, graphene-based materials and liquid-metal interfaces may improve heat transfer in selected applications, but every material must satisfy manufacturing, contamination and reliability requirements.
Thermal management can no longer be added after the electrical architecture is complete. Engineers must evaluate chiplet placement, power delivery, heat paths and mechanical stress together. The arrangement that creates the shortest electrical connection may not provide the most effective route for removing heat.
This integrated design requirement strengthens the position of electronic design automation providers and engineering teams capable of connecting chip, package and system models. Earlier thermal and mechanical analysis can reduce redesign expenses and identify reliability risks before companies commit to costly manufacturing equipment.
Yield is becoming one of the defining economic factors in advanced semiconductor packaging. In traditional packages, a defect typically affects a single die, but in complex AI packages, failures can impact multiple logic dies and HBM stacks that have already absorbed significant manufacturing costs.
As package architectures become larger and more heterogeneous, every additional die, connection and process step introduces new potential failure points. Manufacturers must detect defective components early and control process variation before additional value is added through stacking and integration.
Known-good-die screening, design-for-test methods, in-line inspection, X-ray imaging, acoustic analysis, electrical testing and traceability systems are therefore essential to maintaining package economics. Testing must be distributed throughout the manufacturing flow rather than limited to final package validation, where failure costs are highest.
The challenge increases as interconnects become smaller and buried within three-dimensional structures, requiring a combination of advanced inspection technologies and data-driven process monitoring. Ultimately, advanced packaging success will depend not only on architectural innovation but also on the ability to achieve predictable, high-volume yields. Companies that improve defect detection, process control and testing capabilities can create significant value across the semiconductor ecosystem, even without producing the core processor dies.
Taiwan remains the centre of advanced AI packaging because TSMC combines leading-edge wafer manufacturing with CoWoS, InFO and SoIC. The company stated in 2025 that it planned 11 wafer-manufacturing facilities and four advanced-packaging facilities in Taiwan. Keeping process development, packaging qualification and volume production within one ecosystem shortens feedback cycles between foundries, equipment companies, substrate suppliers and customers.
The United States is treating packaging as a supply-chain and national-technology priority. In January 2025, the U.S. Department of Commerce announced USD 1.4 billion in final awards for next-generation semiconductor packaging. This included USD 1.1 billion for Natcast to operate advanced-packaging capabilities connected to the National Semiconductor Technology Center and National Advanced Packaging Manufacturing Program.
TSMC’s Arizona expansion includes two advanced-packaging facilities and a major R&D centre. The company has explained that these additions are intended to create a more complete domestic AI semiconductor supply chain rather than limiting U.S. operations to wafer production.
Micron has separately stated that it plans to establish advanced HBM packaging in the United States following completion of its second Idaho fab. Linking memory fabrication, HBM assembly and R&D could reduce supply-chain separation for AI memory products.
Singapore is developing a specialized position in AI-memory packaging. In January 2025, Micron began constructing an approximately USD 7 billion HBM advanced-packaging facility beside its existing operations. Initial operations were scheduled for 2026, with meaningful expansion of advanced-packaging capacity expected from 2027.
Japan’s advantage lies in semiconductor materials and equipment. TSMC’s Japan 3DIC R&D Center works with domestic manufacturers, research institutions and universities on next-generation packaging materials, equipment and production processes. Japan may not match Taiwan’s packaging volume, but its position in chemicals, glass, substrates and precision equipment gives it considerable influence over the advanced packaging supply chain.
South Korea’s packaging strategy is connected to its leadership in advanced memory. Samsung and SK hynix require increasingly sophisticated stacking, hybrid bonding and thermal technologies to maintain HBM performance. Samsung has announced approximately KRW 20 trillion of investment through 2030 in its semiconductor R&D complex, while its packaging roadmap combines logic, memory and chiplet integration.
Malaysia, India and other established assembly locations are seeking to move into higher-value packaging activities. Their existing infrastructure and manufacturing workforces provide a foundation, but advanced packaging requires deeper capabilities in process engineering, substrates, automation, design integration, testing and intellectual property. Expanding conventional assembly capacity is not equivalent to mastering hybrid bonding or large-interposer production.
China is also investing in chiplets, fan-out packaging, 2.5D integration and domestic packaging equipment as export restrictions constrain access to some leading-edge semiconductor technologies. Advanced packaging cannot completely compensate for limited access to the smallest transistor nodes, but it can improve system performance by combining available logic, memory and specialized dies more efficiently.
The regional strategies are complementary rather than identical. Taiwan is scaling commercially proven integration platforms around leading-edge foundry production. South Korea is connecting packaging development to its HBM manufacturing position. Japan is concentrating on materials, glass, precision equipment and collaborative R&D. Singapore is building specialized HBM packaging capacity, while Malaysia and India are using established assembly operations as a base for moving toward higher-value processes. The United States is combining incentives, research infrastructure and domestic capacity investment to reduce the separation between chip design, wafer fabrication and advanced assembly.
These positions should not be evaluated only through announced investment volumes. Leadership in advanced packaging depends on the broader manufacturing ecosystem, including skilled engineering talent, reliable substrate and material suppliers, equipment support capabilities, customer collaboration, and the ability to achieve consistent production yields. Countries that develop fabrication capacity without these supporting capabilities may establish facilities but remain dependent on external technologies, materials and expertise.
Investors, procurement teams and semiconductor executives should focus on operational proof points rather than announced investments alone. Qualified packaging capacity, stable package yields, reliable substrate and HBM supply, and customer validation provide a clearer view of commercial readiness than factory size or equipment installation. For emerging technologies, meaningful progress is demonstrated through production customers, volume shipments, standardized processes and proven reliability. These indicators distinguish technologies moving toward scalable manufacturing from those that remain at the development stage.
The next phase of semiconductor competition will be shaped by three capabilities: qualified packaging capacity, consistent package yields and control over the supporting supplier ecosystem. Interconnect density creates value only when manufacturers can integrate advanced logic and memory at scale without losing economic benefits through defects, thermal limitations or material constraints.
TSMC currently benefits from combining leading-edge fabrication with mature CoWoS and SoIC packaging platforms. Intel is developing an alternative systems-foundry approach through EMIB and Foveros, while memory manufacturers are strengthening packaging strategies around HBM integration. Meanwhile, equipment and materials suppliers are gaining importance as package complexity increases requirements for bonding, inspection, substrates, thermal solutions and process control.
The strongest advanced-packaging players will not be defined by the number of technologies they announce, but by their ability to deliver qualified packages in volume with predictable yield and reliability. The real competitive advantage lies in converting complex customer designs into manufacturable systems where advanced dies can operate together efficiently and profitably.
Sources:
Synopsys—What Is Advanced Semiconductor Packaging?
Lam Research—What Is Advanced Packaging?
Lam Research—Why Panel-Level Processing Could Transform Advanced Packaging
TSMC—CoWoS Technology
TSMC—SoIC Technology
TSMC—First-Quarter 2025 Earnings Transcript
Intel Foundry—Advanced Packaging Innovations
Applied Materials—Strategic Investment in Besi
UCIe Consortium—Specifications; Imec—Optical Interconnect Research
U.S. Department of Commerce—Advanced Packaging Awards
Micron—Singapore HBM Advanced Packaging Facility
TSMC—Japan 3DIC R&D Center.